The present invention relates to discharging of flash memory array wells containing memory transistors after an erase operation.
The operation of flash memory transistors is well know in the art. Flash memory transistors are typically arranged in row and column in memory bank arrays in a flash memory device. Each of the memory banks has the associated flash transistors fabricated within a doped conductivity well. For example, N-channel memory transistors are typically fabricated in a p type conductivity well (p well).
FIG. 1 illustrates a conventional N-channel flash memory transistor 25 provided in a p-well 35 of a substrate 11 of a flash memory device. The transistor 25 includes drain 13 and source 15 regions of n+ conductivity provided in the p-well 35. The gate structure of the transistor 25 includes tunnel oxide 17, floating gate 19, a dielectric, e.g., an ONO layer, 21, and a control gate 23. Also shown in FIG. 1 are a bit line 27 which connects to the drain region and a ground line 29 which connects with the source region 15.
During an erase operation for a memory device containing the transistor 25, the array p-well 35, which is typically at ground potential is elevated to an erase voltage of typically eight volts or higher. After the erase voltage is applied, the p-well 35 must be brought back to a ground level as quickly as possible for subsequent memory operations.
However, to pull p-well 35 to ground after a memory operation typically requires an NMOS transistor. Unfortunately, the voltages used for an erase operation typically exceed the snap back voltage of NMOS transistors.
FIG. 4 illustrates the snap-back characteristic of an NMOS transistor where the snap-back effect is observed at a voltage of 5.5 volts. Using such a transistor to discharge a voltage greater than 5.5 volts causes erratic and possibly catastrophic operation of the transistor which makes it difficult to quickly or reliably discharge the erase voltage applied to the p-well 35.
Accordingly, elaborate discharge circuits are required to discharge the p-well well to ground to avoid the snap back problem of NMOS transistors.
It would be desirable to provide a simplified way to discharge the erase voltage quickly and reliably without requiring a complex discharge circuit.
The present invention provides a simple method and apparatus which employ a discharge circuit for discharging the erase voltage applied to an array well of a flash memory device. The discharge circuit includes a main discharge circuit for discharging an array well to ground using an n-channel transistor which may be subject to a snap-back effect due to the applied erase voltage. Accordingly, this transistor is held in an off state until an auxiliary discharge circuit of the discharge circuit first discharges the p-well array voltage to a level below a voltage which will induce the snap-back of the main discharge circuit n-channel transistor. When the erase voltage has been reduced to below the snap back voltage by the auxiliary discharge circuit, the NMOS transistor of the main discharge circuit is turned on to quickly bring the remaining erase voltage on the array well to ground.
In an exemplary embodiment, the main discharge circuit comprises the n-channel transistor which is subject to a snap-back effect at a predetermined voltage level, and the auxiliary discharge circuit comprises a p-channel transistor circuits, or a plurality of p-channel transistor circuits operating in parallel.
The method and apparatus of the invention can be applied to a flash memory device having plural banks of memory arrays, with the transistors of each bank having their own array p-well and with each array p-well having a respective discharge circuit.
These and other objects, advantages and features of the invention will be more clearly understood from the following detailed description of the invention which is provided in connection with the accompanying drawings.